Aim
– (a) Analysis of CMOS inverter
using step input.
(b) Transient Analysis of CMOS
inverter using step input with
parameters.
(c) Transient Analysis of CMOS
inverter using pulse input.
(d) Transient Analysis of CMOS
inverter using pulse input with
parameters.
(e) DC Analysis (VTC) of CMOS
inverter with and without
parameters.
Simulator Used – PSpice.
Theory – CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor. CMOS uses
complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor
field effect transistors (MOSFETs) for logic functions.
When input is HIGH, the gate of PMOS is at 0V
relative to its source i.e. VGS1 =0V. Thus, PMOS is OFF.
On the other hand, the gate of NMOS is at + VDD relative to its source i.e. VGS2 =
+ VDD. Thus, NMOS is ON. This will produce Vout ≈ 0
V.
When input is LOW, the gate of PMOS is at a
negative potential relative to its source while NMOS has VGS = 0 V. Thus, PMOS is
ON and NMOS is OFF. This produces output voltage approximately + VDD.
Digital inverter quality is often measured using
the Voltage Transfer Curve (VTC), which is a plot of input vs. output voltage. Ideally,
the voltage transfer curve (VTC) appears as an inverted step-function - this
would indicate precise switching between on and off - but in real devices, a gradual transition region
exists. The VTC indicates that for low input voltage, the circuit outputs high
voltage; for high input, the output tapers off towards 0 volts. The slope of
this transition region is a measure of quality - steep (close to -Infinity)
slopes yield precise switching.
Circuit Diagram
–
Result –
Conclusion
- (a)
Analysis of CMOS inverter using step input.
(b) Transient Analysis of CMOS
inverter using step input with
parameters.
(c) Transient Analysis
of CMOS inverter using pulse input .
(d) Transient Analysis
of CMOS inverter using pulse input with
parameters.
(e) DC Analysis (VTC) of CMOS inverter
with and without
parameters.
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